3 ms·

I wonder if anyone has been working on disabling PSP[1] the way that people have done with IME. It looks like it's had at least a couple of vulnerabilities [2].

I wonder if anyone has been working on disabling PSP[1] the way that people have done with IME. It looks like it's had at least a couple of vulnerabilities [2]. 1. https://libreboot.org/faq.html#amd https://libreboot.org/faq.html#amd 2. https://en.wikipedia.org/wiki/AMD_Platform_Security_Processor#Security_history https://en.wikipedia.org/wiki/AMD_Platform_Security_Processo...

sodality2 5y ago
Both of my devices' BIOS have an option to "disable AMD PSP". Can't really verify that it's off, though.
- garaetjjte 5y ago
  That's switch for TPM features only. You cannot disable PSP as it is responsible for x86 initialization. https://www.youtube.com/watch?v=bKH5nGLgi08 https://www.youtube.com/watch?v=bKH5nGLgi08
  - matthewfcarlson 5y ago
    Right. Intel platforms do XIP to get through memory training but AMD relies on the PSP to train memory and setup other systems. So without the PSP it just wouldn’t boot.
    - salawat 5y ago
      Sounds like a job for refactoring. Admittedly, I'm mystified what this "memory training" even is. POST->BIOS/UEFI->handoff to OS bootloader... Where's this memory training fit in?
      - jabl 5y ago
        > I'm mystified what this "memory training" even is. Modern high speed links are very finicky, to the extent that various parameters (timing, etc.) on each end of the link can't be hardcoded. The link training is part of initializing the link where the FW on each end of the link try out various parameters in order to enable full speed operation. > Where's this memory training fit in? I believe it happens even before POST.
        rcxdude 5y ago
        > Modern high speed links are very finicky, to the extent that various parameters (timing, etc.) on each end of the link can't be hardcoded. The link training is part of initializing the link where the FW on each end of the link try out various parameters in order to enable full speed operation. Exactly. Initialising DDR memory in any kind of system is a bit of a black art for this reason, even when the chips are soldered to the same PCB as the SOC, let alone when there's two unknown PCBs and two sockets in the mix.
        dfox 5y ago
        On essentially every PC that supports different sizes of RAM modules the firmware has to jump through somewhat interesting hoops in order to configure/enable the memory controller. DDR4 training is just one part of this. Typical flow goes something like this: * All cores are brought out of reset. All cores start executing code from the end of 32b physical address space, hopefully some EPROM with firmware lives there. (One thing of note is that yes, intel says that there is no such thing as "unreal mode", but everything after i386 boots into unreal mode) * Initial state of EDX signifies the position of CPU in SMP system, one core is designated as system processor, all other are application processors and thus do minimal APIC initialization and then enter halt and wait for IPI. * The system processor continues executing its firmware and its first order of bussiness is to configure cache controllers as to get even a few kilobytes of writable SRAM for its data area. * SP initializes enough of on-board PCIe devices to be able to access SMBus/SPD * SP scans SPD to get list of populated DIMMs, their sizing and timing * SP converts the SPD data into memory controller configuration and writes it there (note that at this point we are still doing XIP from slow-ish SPI Flash and have no RAM to speak of, so code that does this has to be very efficient, which is the reason for various RAM incompatibilities, as somehow common approach is to just hardcode expected configurations into the firmware). * SP looks into NVRAM if the DIMM configuration is same as was on previous boot, if it is it skips the next step * If it changed the SP enters the DDR4 link training algorithm. This essentially involves measuring lengths of wires from memory controller to individual DRAM chips. The idea there is that it is impossible to make them well-enough matched for the frequencies involved, so the deliberate difference is compensated for in logic and software (also it saves space on PCB of both motherboard and the DIMMs themselves). * The result of training is written into configuration registers of the DRAM chips and memory controller (and saved into NVRAM for next boot, as the training is somewhat slow) * We have RAM. * Firmware completes initialization of PCIe topology, enables LPC bridge. * Firmware does PCI(e) resource allocation. (The "PNP OS installed" switch in many BIOS configurations controls whether it configures all PCI devices or only these that it deems relevant) * We have something that looks like PC. * What one would call traditional PC-style POST happens now. First phase of ROM SCAN (in BIOS/CSM case) causes the VGA controller to come out of reset. Display turns on and user sees something like "Copyright (C) NVidia/AMD" in top-left corner * Firmware draws its splashscreen/UI. * Firmware completes all other initialization tasks (now running in somewhat sane environment). This involves entering protected mode and in CSM/BIOS case exiting it again (sometimes even multiple times). Various datastructures that are going to be passed to OS get filled in. List of boot devices is built. (this is the step that user perceives as "POST") * Bootloader gets loaded from whatever device was selected and control is passed to it. [Edit: and to make it even more interesting modern CPUs often need microcode update to be applied somewhere pretty early along this process] [Edit2: it is my understanging that on at least some x86 server platforms the memory initialization is done by BMC although I'm not sure how exactly that works... bitbanging the DDR4 controller over JTAG?]
  - sodality2 5y ago
    I am pretty sure that switch just ignores PSP after boot; ie neutering it after it's necessary

sodality2 5y ago

Both of my devices' BIOS have an option to "disable AMD PSP". Can't really verify that it's off, though.

garaetjjte 5y ago
That's switch for TPM features only. You cannot disable PSP as it is responsible for x86 initialization. https://www.youtube.com/watch?v=bKH5nGLgi08 https://www.youtube.com/watch?v=bKH5nGLgi08
- matthewfcarlson 5y ago
  Right. Intel platforms do XIP to get through memory training but AMD relies on the PSP to train memory and setup other systems. So without the PSP it just wouldn’t boot.
  - salawat 5y ago
    Sounds like a job for refactoring. Admittedly, I'm mystified what this "memory training" even is. POST->BIOS/UEFI->handoff to OS bootloader... Where's this memory training fit in?
    - jabl 5y ago
      > I'm mystified what this "memory training" even is. Modern high speed links are very finicky, to the extent that various parameters (timing, etc.) on each end of the link can't be hardcoded. The link training is part of initializing the link where the FW on each end of the link try out various parameters in order to enable full speed operation. > Where's this memory training fit in? I believe it happens even before POST.
      - rcxdude 5y ago
        > Modern high speed links are very finicky, to the extent that various parameters (timing, etc.) on each end of the link can't be hardcoded. The link training is part of initializing the link where the FW on each end of the link try out various parameters in order to enable full speed operation. Exactly. Initialising DDR memory in any kind of system is a bit of a black art for this reason, even when the chips are soldered to the same PCB as the SOC, let alone when there's two unknown PCBs and two sockets in the mix.
      - dfox 5y ago
        On essentially every PC that supports different sizes of RAM modules the firmware has to jump through somewhat interesting hoops in order to configure/enable the memory controller. DDR4 training is just one part of this. Typical flow goes something like this: * All cores are brought out of reset. All cores start executing code from the end of 32b physical address space, hopefully some EPROM with firmware lives there. (One thing of note is that yes, intel says that there is no such thing as "unreal mode", but everything after i386 boots into unreal mode) * Initial state of EDX signifies the position of CPU in SMP system, one core is designated as system processor, all other are application processors and thus do minimal APIC initialization and then enter halt and wait for IPI. * The system processor continues executing its firmware and its first order of bussiness is to configure cache controllers as to get even a few kilobytes of writable SRAM for its data area. * SP initializes enough of on-board PCIe devices to be able to access SMBus/SPD * SP scans SPD to get list of populated DIMMs, their sizing and timing * SP converts the SPD data into memory controller configuration and writes it there (note that at this point we are still doing XIP from slow-ish SPI Flash and have no RAM to speak of, so code that does this has to be very efficient, which is the reason for various RAM incompatibilities, as somehow common approach is to just hardcode expected configurations into the firmware). * SP looks into NVRAM if the DIMM configuration is same as was on previous boot, if it is it skips the next step * If it changed the SP enters the DDR4 link training algorithm. This essentially involves measuring lengths of wires from memory controller to individual DRAM chips. The idea there is that it is impossible to make them well-enough matched for the frequencies involved, so the deliberate difference is compensated for in logic and software (also it saves space on PCB of both motherboard and the DIMMs themselves). * The result of training is written into configuration registers of the DRAM chips and memory controller (and saved into NVRAM for next boot, as the training is somewhat slow) * We have RAM. * Firmware completes initialization of PCIe topology, enables LPC bridge. * Firmware does PCI(e) resource allocation. (The "PNP OS installed" switch in many BIOS configurations controls whether it configures all PCI devices or only these that it deems relevant) * We have something that looks like PC. * What one would call traditional PC-style POST happens now. First phase of ROM SCAN (in BIOS/CSM case) causes the VGA controller to come out of reset. Display turns on and user sees something like "Copyright (C) NVidia/AMD" in top-left corner * Firmware draws its splashscreen/UI. * Firmware completes all other initialization tasks (now running in somewhat sane environment). This involves entering protected mode and in CSM/BIOS case exiting it again (sometimes even multiple times). Various datastructures that are going to be passed to OS get filled in. List of boot devices is built. (this is the step that user perceives as "POST") * Bootloader gets loaded from whatever device was selected and control is passed to it. [Edit: and to make it even more interesting modern CPUs often need microcode update to be applied somewhere pretty early along this process] [Edit2: it is my understanging that on at least some x86 server platforms the memory initialization is done by BMC although I'm not sure how exactly that works... bitbanging the DDR4 controller over JTAG?]
- sodality2 5y ago
  I am pretty sure that switch just ignores PSP after boot; ie neutering it after it's necessary