While decoding a given x86 instruction is serial, since about 2000 metadata has been added to the L1 instruction cache indicating which bytes start an instructi

While decoding a given x86 instruction is serial, since about 2000 metadata has been added to the L1 instruction cache indicating which bytes start an instruction. So you can start decoding multiple instructions in parallel. Doing the same might be useful on a very wide RISC-V decoder. Not needed for 3 or 4 wide though. This is not very expensive, needing only 1 bit per 16 bits of instruction cache data (6.25% overhead), as RISC-V instructions can only start on 2 byte boundaries. This is quite small compared to the 25% to 30% code size you typically save from using both 2 and 4 byte instructions (30% to 50% more instructions in a cache of fixed size). x86 also uses cache of the micro-ops generated from each instruction, to avoid decoding recently-used instructions at all. That's completely unnecessary with simple instruction encodings such as RISC-V.