In 32 bit, Thumb2 aka ARMv7 has slightly better code density than RISC-V. In 64 bit, RISC-V has by far the most dense code compared to ARM, x86, POWER or any o

In 32 bit, Thumb2 aka ARMv7 has slightly better code density than RISC-V. In 64 bit, RISC-V has by far the most dense code compared to ARM, x86, POWER or any other widely used 64 bit ISA. ARM dropped their 2-byte encodings going from 32 to 64 bit, which hurts them a lot. i386/i686 was reasonably dense, but amd64 needs a lot of REX prefix bytes which increases the code size. RISC-V was always designed to allow for variable instruction lengths. The base instruction set is fixed-length 32 bit -- 30 bit really, as the two LSBs are always '11'. Values of the two LSBs other than '11' were always intended for 16 bit instructions. Encodings with all 1s in the "major opcode" field are reserved to indicate future instructions longer than 32 bits. It's very likely that the first such instructions defined will be 48 bit instructions with 32 bit immediate data. However until now, RISC-V core designers have been strongly resisting adding instructions longer than 32 bits even though software people want them. It might look cleaner to load a 32 bit literal using a single 48 bit instruction instead of two 32 bit instructions, but it might not make for a faster computer.