3 ms·
Ah, that's a super interesting point. My vague recollection is that the size per bit for eDRAM is somewhere between a half and a third that for SRAM (isoprocess
by addaon 5y ago
Ah, that's a super interesting point. My vague recollection is that the size per bit for eDRAM is somewhere between a half and a third that for SRAM (isoprocess), so this would be doubling the cache effective area isoprocess... or probably somewhere between maintaining it and halving it with the move to 7 nm. Still looks like it might be less die space for cache, but not nearly as much as I was thinking as first.
- nullc 5y agoExactly. I'm left wondering if the move off of eDRAM was motivated by improved latency or just unavailability of the technology (or that it hadn't been updated to 7nm).
- addaon 5y agoWas eDRAM ever used for L2? I thought its latency put it firmly in L3/L4 camp.
- nullc 5y agoZ12 had a small (1MB) L2, and a 48MB shared eDRAM L3. In this new chip the L2 replaces the prior L2 and L3. Edit: similar deal for Z14 4MB/4MB L2 + 256MB eDRAM L3.
- Tuna-Fish 5y agoUnavailability. There simply is no process for making the deep trench capacitors that yields in <14nm.