Thinking about this a bit more, I suspect that the answer comes down to the two dies per package. The main distinction between on-die cores and off-die cores is

Thinking about this a bit more, I suspect that the answer comes down to the two dies per package. The main distinction between on-die cores and off-die cores is the difference between L3 (single ejection) and L4 (double ejection), and the main use of die-to-die and package-to-package interconnect is going to be handling the L4 data flow. I bet that the numbers showed that goes from 256MB of cache on die (available for active-use L2 + shared L3) to more didn't make much of a difference; that's a pretty big L3 chunk, after all, and even if the latency for L4 is way higher I bet you're already well into marginal gains. In this case, and assuming that the package is thermally limited, there's no real reason not to go to a smaller die. Even if a 16 core, 512MB cache monster fit on reticle, if there's not much performance gap between that and the actual dual 8 core, 256MB cache system, why not take a yield gain from smaller dice? If this is the case, I'd expect this die to be way smaller than the Z15 processor... < 400 mm^2? Anyone have numbers?