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Reading this over, one striking thing is that in going from 14 nm -> 7 nm, they reduced core count from 12 to 8, and kept total cache per die approximately the
by addaon 5y ago
Reading this over, one striking thing is that in going from 14 nm -> 7 nm, they reduced core count from 12 to 8, and kept total cache per die approximately the same (256 MB L3 + various smaller caches -> 256 MB L2*). Looking at the die shot, there isn't an unusual amount of uncore, so this is either a MUCH smaller processor or a MUCH more complex core. Given that the Z series has never been particularly cost limited and has often pushed reticle size, and that by getting rid of the system controller costs will already be coming down... is this just a super-high transistor count SMT2 core?
- nullc 5y agoIIRC that L3 was eDRAM, so it's a bigger change than you might imagine.
- addaon 5y agoAh, that's a super interesting point. My vague recollection is that the size per bit for eDRAM is somewhere between a half and a third that for SRAM (isoprocess), so this would be doubling the cache effective area isoprocess... or probably somewhere between maintaining it and halving it with the move to 7 nm. Still looks like it might be less die space for cache, but not nearly as much as I was thinking as first.
- nullc 5y agoExactly. I'm left wondering if the move off of eDRAM was motivated by improved latency or just unavailability of the technology (or that it hadn't been updated to 7nm).
- addaon 5y agoWas eDRAM ever used for L2? I thought its latency put it firmly in L3/L4 camp.
- nullc 5y agoZ12 had a small (1MB) L2, and a 48MB shared eDRAM L3. In this new chip the L2 replaces the prior L2 and L3. Edit: similar deal for Z14 4MB/4MB L2 + 256MB eDRAM L3.
- Tuna-Fish 5y agoUnavailability. There simply is no process for making the deep trench capacitors that yields in <14nm.
- addaon 5y agoThinking about this a bit more, I suspect that the answer comes down to the two dies per package. The main distinction between on-die cores and off-die cores is the difference between L3 (single ejection) and L4 (double ejection), and the main use of die-to-die and package-to-package interconnect is going to be handling the L4 data flow. I bet that the numbers showed that goes from 256MB of cache on die (available for active-use L2 + shared L3) to more didn't make much of a difference; that's a pretty big L3 chunk, after all, and even if the latency for L4 is way higher I bet you're already well into marginal gains. In this case, and assuming that the package is thermally limited, there's no real reason not to go to a smaller die. Even if a 16 core, 512MB cache monster fit on reticle, if there's not much performance gap between that and the actual dual 8 core, 256MB cache system, why not take a yield gain from smaller dice? If this is the case, I'd expect this die to be way smaller than the Z15 processor... < 400 mm^2? Anyone have numbers?
- addaon 5y agoFollowup: Looks like 530 mm^2 [1], so quite a bit smaller than Z15 but not by a factor of two; consistent with nullc's eDRAM observation. [1]: https://wccftech.com/ibm-z-next-gen-processor-detailed-telum-chip-7nm-process-22-5-billion-transistors-8-cores-beyond-5-ghz-clocks/ https://wccftech.com/ibm-z-next-gen-processor-detailed-telum...
- IanCutress 5y agoFWIW, the article this thread links to says 530mm2.
- qwertox 5y ago> so this is either a MUCH smaller processor or a MUCH more complex core. According to the video presentation [1] each processor also contains an AI accelerator with more than 1000 compute engines for >6 TFlops [1] https://www.ibm.com/blogs/systems/ibm-telum-processor-the-next-gen-microprocessor-for-ibm-z-and-ibm-linuxone/ https://www.ibm.com/blogs/systems/ibm-telum-processor-the-ne...