No, there are certainly ISA related performance factors. RISC-V compressed instructions are easier to decode than x86 but you still need to detect boundaries a

No, there are certainly ISA related performance factors. RISC-V compressed instructions are easier to decode than x86 but you still need to detect boundaries and mux instructions to their proper lanes. And if you don't you have problems with i-cache pressure. In theory instruction fusion can do a lot to increase backend instruction density. But to equal other ISAs RISC-V have to be fusing triplets instead of just pairs and that's a quadratically harder problem. It's not the end of the world but I don't think it's an accident that x86, on of the simplest CISC ISAs, and ARM, one of the most complex RISC ISAs, ended up being dominant.