It still makes it impossible to trivially parallelise the decoding itself, before even looking at the instructions. x86 CPUs can barely decode in parallel, par

It still makes it impossible to trivially parallelise the decoding itself, before even looking at the instructions. x86 CPUs can barely decode in parallel, partly because the outputs of parallel decoders have to be synced up. A RISC-V core to rival the M1 wouldn’t use instruction compression.