4 ms·
Regardless, any amount of variability restricts parallelism. You can’t split the instruction stream ahead of time into equal portions to hand to many separate d
by lucian1900 5y ago
Regardless, any amount of variability restricts parallelism. You can’t split the instruction stream ahead of time into equal portions to hand to many separate decoding units.
- zozbot234 5y agoFinding out the insn length is a trivial part of decode, unlike in other architectures. If x86 can profitably use "separate decoding units", RV+C will be able to do it to a far greater extent.
- lucian1900 5y agoIt still makes it impossible to trivially parallelise the decoding itself, before even looking at the instructions. x86 CPUs can barely decode in parallel, partly because the outputs of parallel decoders have to be synced up. A RISC-V core to rival the M1 wouldn’t use instruction compression.
- brucehoult 5y agoYes it would. Wait two to three years and you will see.
- trasz 5y agoSure you can, you just need, in worst case, twice the decoders.