4 ms·

That is an implementation detail of the processor hardware, and not of the instruction set, unless you have some details on why RISC-V cannot be implemented thi

by ch_123 5y ago

That is an implementation detail of the processor hardware, and not of the instruction set, unless you have some details on why RISC-V cannot be implemented this way.

ahartmetz 5y ago
It is absolutely a property of the instruction set. In the meantime, I remembered two prominent examples: ARM has compare-and-branch instructions and load / store with offset and scaling instructions. There is no way to get the benefits of less decoding and possibly combining (possibly also reduced register pressure and shorter dependency chains - no intermediate address calculations or comparison status registers) without changing the instruction set.
- zozbot234 5y ago
  RISC-V has compare-and-branch instructions, and load/store instructions w/ an offset field. Scaling can be achieved via insn fusion.
  - ahartmetz 5y ago
    Thanks for the correction. RISC-V actually seems to have the most efficient way to do conditional branches of all common ISAs (according to its instruction set reference document, heh). But about the more complex ARM load/store opcodes, the point stands that instruction fusion does not simplify decoding or increase code density the way a pre-fused instruction does.
    - brucehoult 5y ago
      "pre-fused" instructions use up a lot of opcode space that might be better used for other things. Complex addressing modes help code size if you've got just a single access to an array element in some straight line code, but they're seldom needed in loops because most of the calculation is best moved outside of the loop leaving just a simple pointer increment inside the loop.
- deleted 5y ago
  [deleted]
Symmetry 5y ago
No, there are certainly ISA related performance factors. RISC-V compressed instructions are easier to decode than x86 but you still need to detect boundaries and mux instructions to their proper lanes. And if you don't you have problems with i-cache pressure. In theory instruction fusion can do a lot to increase backend instruction density. But to equal other ISAs RISC-V have to be fusing triplets instead of just pairs and that's a quadratically harder problem. It's not the end of the world but I don't think it's an accident that x86, on of the simplest CISC ISAs, and ARM, one of the most complex RISC ISAs, ended up being dominant.

by ch_123 5y ago

That is an implementation detail of the processor hardware, and not of the instruction set, unless you have some details on why RISC-V cannot be implemented this way.

ahartmetz 5y ago

It is absolutely a property of the instruction set. In the meantime, I remembered two prominent examples: ARM has compare-and-branch instructions and load / store with offset and scaling instructions. There is no way to get the benefits of less decoding and possibly combining (possibly also reduced register pressure and shorter dependency chains - no intermediate address calculations or comparison status registers) without changing the instruction set.

zozbot234 5y ago
RISC-V has compare-and-branch instructions, and load/store instructions w/ an offset field. Scaling can be achieved via insn fusion.
- ahartmetz 5y ago
  Thanks for the correction. RISC-V actually seems to have the most efficient way to do conditional branches of all common ISAs (according to its instruction set reference document, heh). But about the more complex ARM load/store opcodes, the point stands that instruction fusion does not simplify decoding or increase code density the way a pre-fused instruction does.
  - brucehoult 5y ago
    "pre-fused" instructions use up a lot of opcode space that might be better used for other things. Complex addressing modes help code size if you've got just a single access to an array element in some straight line code, but they're seldom needed in loops because most of the calculation is best moved outside of the loop leaving just a simple pointer increment inside the loop.
deleted 5y ago
[deleted]

Symmetry 5y ago

No, there are certainly ISA related performance factors. RISC-V compressed instructions are easier to decode than x86 but you still need to detect boundaries and mux instructions to their proper lanes. And if you don't you have problems with i-cache pressure. In theory instruction fusion can do a lot to increase backend instruction density. But to equal other ISAs RISC-V have to be fusing triplets instead of just pairs and that's a quadratically harder problem. It's not the end of the world but I don't think it's an accident that x86, on of the simplest CISC ISAs, and ARM, one of the most complex RISC ISAs, ended up being dominant.