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GateBoy – A gate-level simulation of the original Game Boy hardware
- warning26 5y ago> Is GateBoy a perfect simulation of a Game Boy? > Actually no, for complicated reasons. The Game Boy chip has a handful of logic gates that operate independently of the master clock and whose exact behavior depends on things like gate delay. These gates create glitches that depend heavily on the physical placement of the gates, the silicon process used to make them, and other weird things like temperature and voltage. This is fascinating, I previously would have assumed that a gate-level simulation would necessarily be perfect by definition.
- aappleby 5y agoAnd incredibly annoying as the developer - so much work translating and debugging gates, and it's still not "correct" for some definition of correct ;)
- deelowe 5y agoDon't be too annoyed. There are significant differences across models and even batches within the same generation of system. There is no completely correct definition of a system.
- mattcurrie 5y agoSome of these differences are CPU observable, so I made this ROM to identify different Game Boy models and revisions: https://github.com/mattcurrie/which.gb https://github.com/mattcurrie/which.gb
- deelowe 5y agoVery cool!
- grp000 5y agoSo is this saying that a possible modern day commercial for a Game Boy might feature: "The artisanal properties of the Nintendo Game Boy make each and every one a unique playing experience!"?
- ceronman 5y agoI guess it's impossible to ever have it correct. The gates are just another level of abstraction. You could also simulate the silicon atoms and the electrons flowing and use that to have transistors and then gates. And so on.
- BoxOfRain 5y agoReminds me of hearing about how Crash Bandicoot was developed, as well as being something of a masterpiece in itself they successfully debugged an issue that caused the memory card to get corrupted when the controller was touched in a certain way. I can't remember the precise reason but they eventually discovered that running one of the chips at a higher frequency introduced subtle electrical interference with nearby components on the board. This was after much debugging for a supposed software issue in the memory card logic. I often think of that when I have a tricky bug to sort out.
- williamdclt 5y agohttps://www.gamedeveloper.com/programming/my-hardest-bug-ever https://www.gamedeveloper.com/programming/my-hardest-bug-eve... A great and short read
- TheJoeMan 5y ago“ This is the only time in my entire programming life that I've debugged a problem caused by quantum mechanics “ Who knows, we may be running into this more literally in our lifetime.
- BoxOfRain 5y agoI suppose all problems of this world are caused by quantum mechanics in a sense.
- hbn 5y agoIf you want a great and long read, Andy Gavin has a pretty extensive series about Crash Bandicoot on his blog, some entries more technical than others. I've never even played the games for more than a few minutes, but I had a great time reading through these https://all-things-andy-gavin.com/video-games/making-crash/ https://all-things-andy-gavin.com/video-games/making-crash/
- deelowe 5y agoI read this as well. I'm definitely referencing this in the future when someone mentions how "FPGAs directly simulate the system hardware."
- aappleby 5y agoAs I understand it asynchronous logic stopped being a common thing decades ago, so those sorts of glitches aren't possible (or less possible?) now. The hard stuff in simulation now is probably handling multiple clock domains.
- deelowe 5y agoI’ve only ever seen behavioral solutions for newer systems. At a certain point, logic level designs become unreasonable.
- photojosh 5y agoStill out there, but only used in special situations. The ARM microcontroller I'm working with has an asynchronous prescaler on the real-time clock crystal input before it gets fed into a second synchronous prescaler which you can then read the output of directly. This is all about reducing power consumption down in the nA range when the CPU is turned off but the RTC keeps ticking over. Multiple clock domains definitely tricky though!
- jasonjayr 5y agoAs a software-only guy .... multiple clock domains sounds like the same class of problem as multi threaded + parallel programming, right?
- aappleby 5y agoSort of? It's almost more equivalent to networking or distributed processing - circuits in different clock domains can't just send a wire to another domain, they have to go through a synchronizer and do some handshaking and other stuff that's vaguely similar to RPCs. I'm stretching here, it's slightly beyond what I've worked with so far.
- flatiron 5y agoIf you simulate cycle accuracy you don’t need to simulate each gate. Think of pins on your cpu and the trillions of gates. If you simulated your cpu you just care what’s at the pins. Not at the gates.
- zamadatix 5y agoThis assumes the gate level implementation doesn't have any side effects that are related to more than an instantaneous state. Seemingly unlikely as that is a larger class than the group of side effects mentioned in the quote above.
- flatiron 5y agoYou are right. You buy nothing other than research for gate level. For accuracy you simply need cycle level (which is nothing easy mind you)
- matheusmoreira 5y ago> These gates create glitches What sort of glitches? Which effects could they produce on outputs? I wish there was a concrete example.
- gambiting 5y agoThere are examples on the github page, literally right below that sentence - have you stopped reading just before that point?? "For example, there's a glitch in the external address bus logic that causes internal bus addresses like 0xFF20 to appear on the external bus even though the logic should prevent that. Due to gate delays, not all of the inputs to gate LOXO (page 8 in Furrtek's schematics) arrive at the same time. This causes LOXO to produce a glitch pulse that in turn causes latch ALOR to make a copy of one bit of the internal bus address. ALOR then drives that bit onto the external bus (through a few more gates) where it can be seen with an oscilloscope or logic analyzer."
- Anunayj 5y agoBtw I'm a little confused, So are these "glitches" reliably same across all game boys or can this differ from chip to chip?
- randomswede 5y agoThey can differ from gameboy to gameboy. And from day to day (as some of them are apparently temperature dependent).
- rot13xor 5y agoLatches or a ring oscillator to generate true randomness. There could also be bugs in the design that cause metastability.
- p4bl0 5y agoThis is also the reason why it is so hard to protect against side channel leakage. During my PhD I worked on a solution that would be theoretically perfect (and is formally proved so), but is not in practice because of exactly that. You can find the paper (Formally Proved Security of Assembly Code Against Power Analysis) and presentation slides on my web page: https://pablo.rauzy.name/research.html#rauzy2014formaldpl https://pablo.rauzy.name/research.html#rauzy2014formaldpl
- jstrieb 5y agoThis is very impressive! The creator—Austin Appleby—also created MurmurHash, which is very useful for data structures like Bloom filters. The canonical MurmurHash implementation was released with a handy non-cryptographic hashing test suite. https://github.com/aappleby/smhasher https://github.com/aappleby/smhasher Thanks for your work, Austin!
- aappleby 5y agoYou are quite welcome. :)
- ArtWomb 5y agoWhoa! This just cements my contention: Nintendo GameBoy should be on every intro to computational architectures syllabus ;)
- aappleby 5y agoI really think it should be, though I'd put a Risc-V RV32I core in place of the original one.
- professoretc 5y agoWriting Hello World for the original GameBoy is a module in the architecture course I teach.
- throwyanope 5y agoWould this ever make it into the MiSTer FPGA project as a core? There is currently a GB core included, but I'm not sure whether the VHDL is a 1:1 mapping to the actual HW gates themselves.
- aappleby 5y agoThe cores they have are more than good enough. I do intend to get GateBoy to where it can be automatically translated to Verilog though, at which point running on a FPGA should be more straightforward.
- deleted 5y ago[deleted]
- modeless 5y agoThis is awesome stuff Austin! > GateBoy, LogicBoy, and MetroBoy exist to give me a starting point for working on Metron, which is my long-term project to build a set of programming tools that can bridge between the C/C++ universe used by software and the Verilog/VHDL universe used by hardware. I'd love more details about this. What does it mean to bridge C/C++ and Verilog/VHDL?
- flatiron 5y agoAnyone who wants the “typescript” of verilog should check out https://en.m.wikipedia.org/wiki/Chisel_(programming_language) https://en.m.wikipedia.org/wiki/Chisel_(programming_language... Makes life’s 100x easier
- aappleby 5y agoEasier than VHDL, harder than C. Chisel's "adder" example on the wikipedia page is: class Add extends Module { val io = IO(new Bundle { val a = Input(UInt(8.W)) val b = Input(UInt(8.W)) val y = Output(UInt(8.W)) }) io.y := io.a + io.b } whereas the same in C would be uint8_t Add(uint8_t a, uint8_t b) { return a + b; } and while that is not directly usable in SystemVerilog, it can be mechanically translated to function byte add(byte a, byte b) return a + b; endfunction There's way more to it than that, but I strongly believe there are better ways of writing hardware than the existing HDLs.
- flatiron 5y agoHonestly from the chisel and C example I can’t really see much a difference. Not sure why corporate it making me choose. That io bundle in your first example is defined in place and then used. If that was previously defined (which would be a shitty Wikipedia example) it would look a lot like your C example.
- artemonster 5y agoImho, you‘re barking at the wrong tree. Design with existing HDLs is a solved problem. Verification is not :)
- Keyframe 5y agoAmazing work. Congratulations on endurance!
- UncleOxidant 5y agoThat had to require a huge amount of endurance, perseverance, etc. I'd like to see a story on how he kept motivated and focused on this project.
- aappleby 5y agoFamily tragedy and pandemic, no lie. Working on it kept me sane.
- barosl 5y agoWhat a marvelous project! The amount of efforts that the author put into this project makes my jaw drop. This project reminds me of a question I've had in my mind, though. If this world is a simulation, would that be an accurate simulation of the elementary particles and their interactions (like this project), or an appropriated one (like normal Game Boy emulators)?
- aappleby 5y agoFurrTek deserves as much credit as I do for doing the initial exceptionally painstaking step of marking out the die traces and cells on the die shot. Not all of his guesses were correct, but they were enough to get things started. I suspect that this world is a high-level simulation until you pull out a microscope, at which point it switches to low-level mode. ;)
- arduinomancer 5y agoAh yes the real life LOD system
- all2 5y agoI read somewhere (I'll dig for the article) that one of the conclusions of Quantum mechanics was that "things don't exist unless you look at them". And the claim was that this actually happened on the macro level. This is one of many articles that discusses the experiment: https://www.sciencealert.com/reality-doesn-t-exist-until-we-measure-it-quantum-experiment-confirms https://www.sciencealert.com/reality-doesn-t-exist-until-we-...
- mysterydip 5y agoI was under the impression the gameboy cpu was a standard z80, but it seems that's not the case? What did they add to it?
- aappleby 5y agoThey removed some instructions and added some instructions. Check the pandocs - https://gbdev.io/pandocs/ https://gbdev.io/pandocs/
- ekimekim 5y agoThe Gameboy CPU is signifigantly less capable than a full z80. It's missing key features like the IX and IY registers (and thus addressing modes), most of the 16-bit ALU, the second set of "shadow" registers intended for interrupt handling (instead, almost all gameboy interrupt routines start by pushing all the current registers onto the stack), and a bunch of other things I forget. There's also some stuff it adds, such as the swap instruction (swapping the upper and lower nibbles of a byte) and the stop instruction (puts the gameboy into a low-power state until it is woken by a keypress).
- userbinator 5y agohttps://gbdev.gg8.se/wiki/articles/CPU_Comparision_with_Z80 https://gbdev.gg8.se/wiki/articles/CPU_Comparision_with_Z80 They added/changed/removed instructions to fit the system more closely, e.g. IN/OUT is now done through MMIO in the FFxx area and thus there are dedicated instructions to access that address range.
- userbinator 5y agoSince logic simulation is a massively parallel task, I wonder how much faster it would be if you used the GPU to do it. Funny to see the gates named "DEFY", and "CYKA" right below it...
- thechao 5y agoYou either sort by cone, getting great gate-value reuse density, but lose gobs of parallelism; or, you sort by gate-type & eat-shit on gather-scatter. It’s a devil’s bargain, either way. It’s why the majors sell $$$…$$$ custom emulation equipment. It’s also a field long overdue for disruption.
- mschuster91 5y ago> It’s also a field long overdue for disruption. Won't happen though, way too niche market - outside of a single-digit number of hobbyists, the only ones who have an actual use for such equipment are companies for whom the expense is a rounding error on the balance sheet.
- ip26 5y agoDoesn’t avx offer bitwise logical operations? Pack your wires into avx vectors.
- CultMember002 5y agoWe should not allow the Fed to stifle innovation and technological progress. If we are not willing to take risks, then we will never be able to reach our true potential of becoming a truly advanced space faring civilization and a multi-planetary species. The NHTSA does not have the technological capability to understand advanced AI used in Autopilot and Full Self Driving and they should stop their interference immediately. I have a Tesla and I bought the Full Self Driving package. I believe it is far more valuable than the current price. I am willing to pay 30 times more for Full Self Driving.
- piyh 5y agoI've heard family talk about chip design and verilog. This is the first time i feel like I've had a glimpse into what they're talking about. Great write up.
- GauntletWizard 5y agoThis is awesome!