> AMD CPUs may transiently execute non-canonical loads and store using only the lower 48 address bits, potentially resulting in data leakage. In post-Spectre/M

> AMD CPUs may transiently execute non-canonical loads and store using only the lower 48 address bits, potentially resulting in data leakage. In post-Spectre/Meltdown era, seems like every innocent optimization can be used as side channels, and as a result, must be disabled. It makes me a little sad that, nobody knows how much more performance tax we will have to pay in the future for the ability of safely running untrusted code in a "sandbox" (be it hypervisor, user-kernel separation or Javascript VM).