A large part of modern chip design is accomplishing what you are trying to do inside a given power budget. Thus, anything that lowers power is usually a huge wi

A large part of modern chip design is accomplishing what you are trying to do inside a given power budget. Thus, anything that lowers power is usually a huge win. Switching power in CMOS is roughly proportional to V^2 (basic textbook, real design includes a vastly larger number of issues), so lowering V is a huge win. Also, reducing the parasitic cap with a better process is a big win for a multitude of reasons. But shrinking the process generally would require the voltage to scale also because the gate oxide was getting thinner. That is not really true any more as we reach supply voltages that are so close the Von of the devices, but used to be a clear trend. High voltages are good when you want to deliver power because that is what you need (motor HP, space heater, etc.). But we don't use an IC for power, we use it to do logic, and in that case, logic is just much more efficient at low voltages.