> So currently chips are printed into regions that are limited in size by physics, to a 3cm square. It's not quite that direct a limit. While performance almo

> So currently chips are printed into regions that are limited in size by physics, to a 3cm square. It's not quite that direct a limit. While performance almost always wants bigger chips there are counterbalancing forces (yield and heat dissipation) that want smaller chips. Chip manufacturing is (roughly) limited by defects until you reach the physical size of a wafer. The larger your chip the more likely that some critical circuit hits/has a defect and fails. For example, if a wafer has 10 defects, but you are producing 1500 chips then at worst you will get a yield of 99%. If you are producing 100 bigger chips, you may get a yield of 90%. If you are only producing 10 (big!) chips, you may get a yield of 0%. This drops as the square of the chip dimension. After you manufacture the chip, chip size is limited by power distribution and heat dissipation. The bigger your chip the more it needs of both until you can't supply it or cool it anymore. This is why "3D" chips don't really win--getting power in and heat out scales as surface area--not volume.