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So currently chips are printed into regions that are limited in size by physics, to a 3cm square. And processing power is traditionally increased by stacking th

So currently chips are printed into regions that are limited in size by physics, to a 3cm square. And processing power is traditionally increased by stacking them in upto a dozen layers that are interconnected at the edges. Here, instead of that, the circuits are overlap-printed so that a single wafer can support a set of 80 connected circuits, which are now physically cooleable because of the flat design? While they must be sacrificing some interconnection richness, because of geometrical placement, for AI applications this probably doesn’t matter so much. Very interesting.

bsder 5y ago
> So currently chips are printed into regions that are limited in size by physics, to a 3cm square. It's not quite that direct a limit. While performance almost always wants bigger chips there are counterbalancing forces (yield and heat dissipation) that want smaller chips. Chip manufacturing is (roughly) limited by defects until you reach the physical size of a wafer. The larger your chip the more likely that some critical circuit hits/has a defect and fails. For example, if a wafer has 10 defects, but you are producing 1500 chips then at worst you will get a yield of 99%. If you are producing 100 bigger chips, you may get a yield of 90%. If you are only producing 10 (big!) chips, you may get a yield of 0%. This drops as the square of the chip dimension. After you manufacture the chip, chip size is limited by power distribution and heat dissipation. The bigger your chip the more it needs of both until you can't supply it or cool it anymore. This is why "3D" chips don't really win--getting power in and heat out scales as surface area--not volume.