> It sounds like you're thinking of virtual memory (i.e. pages of memory either being in RAM or on disk). I think I mostly just used the wrong term (page inste

> It sounds like you're thinking of virtual memory (i.e. pages of memory either being in RAM or on disk). I think I mostly just used the wrong term (page instead of line) -- I'm on board with the distinction you're drawing. > But if you're unlucky and they are fighting for the same cache line, then each access can end up evicting the previous one and forcing a main memory look up for every single component. Yeah, I think this specifically is what I'm having a hard time imagining. I guess it depends on how which memory regions get mapped into which cache lines, and I think I'm assuming something closer to fully-associative, while you're allowing for something closer to direct-mapped. I can see the trouble -- you don't really have much control over the mapping, unless you make some really deep assumptions about the CPU architecture and go to great lengths to position your arrays appropriately in memory. That would certainly be in the original spirit of data-oriented design, but it's perhaps a bit beyond reasonable for most systems. Thanks for working through this with me! (P.S. For others, I found this illustration that helped load a bit of CPU cache architecture back into my brain: http://csillustrated.berkeley.edu/PDFs/handouts/cache-3-associativity-handout.pdf http://csillustrated.berkeley.edu/PDFs/handouts/cache-3-asso...)