3 ms·
You should be able to use some kind of coloring approach to avoid that kind of false sharing, right?
by quotemstr 5y ago
You should be able to use some kind of coloring approach to avoid that kind of false sharing, right?
- gugagore 5y agoI don't think this is false sharing since the issue can occur without any writes.
- munificent 5y agoI'm not an expert at the details of hardware architecture, but my understanding is that you're basically stuck with whatever associativity and cache policy the chip supports. That, and the addresses that your components happen to be at, will determine whether they end up fighting over cache lines or not. https://en.wikipedia.org/wiki/Cache_placement_policies https://en.wikipedia.org/wiki/Cache_placement_policies
- renox 5y ago'false sharing' == two items next to another in memory are accessed by different thread, as they are closed in memory they are then in the same cache line which is 'shared' between two CPUs: read only is okay but read&write is a performance killer Here it's a cache (associativity) conflict, as gugagore said it can impacts performance even in read only situation.. And yes, you're describing a way to avoid the conflicts.