3 ms·

I wonder how much performance hit you get by enabling 57-bit virtual address space. One could imagine this could hurt very random access patterns due to extra l

• monocasa 5y ago
  Ostensibly your working set should be in your TLBs either way. If you're thrashing your TLB and causing page table walks regularly, 5 versus 6 memory accesses per fetch is rough regardless. If that's showing up in your profiler traces you should start looking at techniques like huge pages to better fit within your TLBs. You can see this in how, at worse case, a hardware virtualized page table walk can take 20 memory accesses by my count if it completes without trapping, Host addresses will by definition all reference the same PML4, so that'll be cached, but everything else could have to go all the way out to DRAM. In practice the overhead of that is typically in the low single digit percentage range.
  • monocasa 5y ago
    Blergh, I thought about it wrong, it's worse than 20. Obviously the whole PML4 isn't guaranteed to be cached.