4 ms·

I wish I knew which parts Linus was talking about. Segmented addressing? Can't be that. Assymetric registers? Probably not that. Vitual 86 mode? Meh. Variable i

I wish I knew which parts Linus was talking about. Segmented addressing? Can't be that. Assymetric registers? Probably not that. Vitual 86 mode? Meh. Variable instruction length? God I hope not. Begs the question: what oddities? I think this is the most astute statement he makes: "yeah, and the fact that they are everywhere." > ARM's Johnny-come-lately 64-bit implementation that has gone farther up and down What do you mean? Arm is primarily embedded IP, where 64b only recently has come en vogue (unless you mean A5/A7?, I'm talking Cortex-M). Arm competitors are really Renesas, Synopsys, TI, and a number of Chinese chips, and 64b isn't a prioirity in most of that space. Not defending anyone, just not sure what you mean.

chasil 5y ago
Could Itanium have done this? https://www.arm.com/blogs/blueprint/fujitsu-a64fx-arm https://www.arm.com/blogs/blueprint/fujitsu-a64fx-arm
- SavantIdiot 5y ago
  Probably not: this is a boutique machine defined with an esoteric architecture, not a general-purpose integer computer for the cloud, which I was what I was talking about in my grand-parent-comment.
  - chasil 5y ago
    Perhaps the key point is the era of design. The P4 was built with an enormous pipeline (~20 stage?) in the hopes of reaching a 10ghz goal that was never going to happen. The Itanium was designed a decade before, programmed for parallelism that was also never going to happen. The M1 is not an esoteric machine, and if Apple had bundled an Itanium of equal computational ability, all of those NOPs would burn a hole through the casing. ARM's 64-bit implementation is obviously something special, esoteric or not it is more powerful than anything produced by Intel in several measures.
    - SavantIdiot 5y ago
      Did HP really start that VLIW design _TEN_ years before P4, because that would be 1985 and I find that unlikely? At Intel IA64 and P4 were developed at the about same time, with P4 taping-out a few years later; the former in Santa Clara, the latter in Oregon. > The M1 is not an esoteric machine, and if Apple had bundled an Itanium of equal computational ability, all of those NOPs would burn a hole through the casing. You're right, its not. And I never said it was. But a 6D mesh torus sure is.
lizknope 5y ago
Did you read the post you are replying to? Linus says to ignore the design mistakes like segmentation. Then he says: "the baroque instruction encoding on the x86 is actually a _good_ thing: it's a rather dense encoding, which means that you win on icache."
- SavantIdiot 5y ago
  Oh, I don't think the link was originally there, or I missed it. Yes, of course: that claim is like the first shot across the bow in every CISC vs. RISC debate.
- FullyFunctional 5y ago
  He did say that and he's wrong. x86 isn't particularly dense and RISC-V compressed is denser. However the insane encoding is burning real power, takes up real area, and is a real limiter for decoding. Dear Linus has an irrational love for x86.
  - lizknope 5y ago
    He wrote those comments in 2003. The instruction decode logic takes up less space with each new chip and process shrink. These days I don't think it really matters much.
    - FullyFunctional 5y ago
      It does. Source: Intel engineering, privately off the record. How wide is the widest Intel CPU? How wide is M1? Case closed.
Symmetry 5y ago
Linus is a big fan of rep movs.

chasil 5y ago

Could Itanium have done this? https://www.arm.com/blogs/blueprint/fujitsu-a64fx-arm https://www.arm.com/blogs/blueprint/fujitsu-a64fx-arm

SavantIdiot 5y ago
Probably not: this is a boutique machine defined with an esoteric architecture, not a general-purpose integer computer for the cloud, which I was what I was talking about in my grand-parent-comment.
- chasil 5y ago
  Perhaps the key point is the era of design. The P4 was built with an enormous pipeline (~20 stage?) in the hopes of reaching a 10ghz goal that was never going to happen. The Itanium was designed a decade before, programmed for parallelism that was also never going to happen. The M1 is not an esoteric machine, and if Apple had bundled an Itanium of equal computational ability, all of those NOPs would burn a hole through the casing. ARM's 64-bit implementation is obviously something special, esoteric or not it is more powerful than anything produced by Intel in several measures.
  - SavantIdiot 5y ago
    Did HP really start that VLIW design _TEN_ years before P4, because that would be 1985 and I find that unlikely? At Intel IA64 and P4 were developed at the about same time, with P4 taping-out a few years later; the former in Santa Clara, the latter in Oregon. > The M1 is not an esoteric machine, and if Apple had bundled an Itanium of equal computational ability, all of those NOPs would burn a hole through the casing. You're right, its not. And I never said it was. But a 6D mesh torus sure is.

lizknope 5y ago

Did you read the post you are replying to? Linus says to ignore the design mistakes like segmentation. Then he says: "the baroque instruction encoding on the x86 is actually a _good_ thing: it's a rather dense encoding, which means that you win on icache."

SavantIdiot 5y ago
Oh, I don't think the link was originally there, or I missed it. Yes, of course: that claim is like the first shot across the bow in every CISC vs. RISC debate.
FullyFunctional 5y ago
He did say that and he's wrong. x86 isn't particularly dense and RISC-V compressed is denser. However the insane encoding is burning real power, takes up real area, and is a real limiter for decoding. Dear Linus has an irrational love for x86.
- lizknope 5y ago
  He wrote those comments in 2003. The instruction decode logic takes up less space with each new chip and process shrink. These days I don't think it really matters much.
  - FullyFunctional 5y ago
    It does. Source: Intel engineering, privately off the record. How wide is the widest Intel CPU? How wide is M1? Case closed.

Symmetry 5y ago

Linus is a big fan of rep movs.