3 ms·

This is exactly right. I really like the Cortex-M4 line as they have lots of peripherals, flash, and some have DDR controllers that will drive megabytes of RAM.

This is exactly right. I really like the Cortex-M4 line as they have lots of peripherals, flash, and some have DDR controllers that will drive megabytes of RAM. On a cycle by cycle basis they are roughly 10x the performance of an Intel 80286, the chip in the PC/AT.

userbinator 5y ago
On a cycle by cycle basis they are roughly 10x the performance of an Intel 80286, the chip in the PC/AT. ...so roughly similar to an Intel Pentium (P5).
- ChuckMcM 5y ago
  Yes, but without the pipeline and the complex instruction set! That said, it will be interesting when one of these SOC vendors decides to make a 'south bridge' serial I/O bus (I'm thinking like four LVDS channels clocked at 100MHz)which then connects to a selection of peripheral modules. That would give customers a 2 chip solution that could have a lot more variety than trying to stock 100+ SKUs to meet various market needs.
  - girvo 5y ago
    Any idea why it hasn't been attempted yet by one of these vendors?
    - ChuckMcM 5y ago
      If things are anything at all like they were when I was at Intel then it is an inability to handle risk. Wafer starts are expensive, masks are expensive, margins on this sort of processor are tight. Basically that adds up to nobody wanting to be "that guy" (and it is always a guy) who pushes through the idea that costs the company a few million dollars. As a result, unless some customer both specifically asks for this, and commits to enough volume to insure that they will at least break even, they aren't going to risk it.
  - userbinator 5y ago
    'south bridge' serial I/O bus (I'm thinking like four LVDS channels clocked at 100MHz) You mean something like https://en.wikipedia.org/wiki/Direct_Media_Interface https://en.wikipedia.org/wiki/Direct_Media_Interface ?
    - ChuckMcM 5y ago
      Yes, although I'd go with the original (and simpler) Intel Hub Architecture concepts. Interestingly enough you can do this on your own using the RISC-V architecture and FPGA's with high speed serial transceivers. So it isn't like you have to be a chip company to build something like it, it just means you're willing to spend way more to implement a RISC-V system than you technically "have" to :-). Esden tweeted today (https://twitter.com/esden/status/1420498544960557062 https://twitter.com/esden/status/1420498544960557062) they have Linux running on the ICE40UP5K which is pretty amazing. That FPGA only has a few LVDS pins so it would be challenging!
pjmlp 5y ago
Indeed, that is why when people think the only way to code these chips is Assembly and C, while we were already using multiple languages on the PCs, shows how there is some kind of misunderstanding of their capabilities. Heck, compiled xBase applications were hardly a speed daemon, yet they were fast enough for what businesses needed of them.

userbinator 5y ago

On a cycle by cycle basis they are roughly 10x the performance of an Intel 80286, the chip in the PC/AT. ...so roughly similar to an Intel Pentium (P5).

ChuckMcM 5y ago
Yes, but without the pipeline and the complex instruction set! That said, it will be interesting when one of these SOC vendors decides to make a 'south bridge' serial I/O bus (I'm thinking like four LVDS channels clocked at 100MHz)which then connects to a selection of peripheral modules. That would give customers a 2 chip solution that could have a lot more variety than trying to stock 100+ SKUs to meet various market needs.
- girvo 5y ago
  Any idea why it hasn't been attempted yet by one of these vendors?
  - ChuckMcM 5y ago
    If things are anything at all like they were when I was at Intel then it is an inability to handle risk. Wafer starts are expensive, masks are expensive, margins on this sort of processor are tight. Basically that adds up to nobody wanting to be "that guy" (and it is always a guy) who pushes through the idea that costs the company a few million dollars. As a result, unless some customer both specifically asks for this, and commits to enough volume to insure that they will at least break even, they aren't going to risk it.
- userbinator 5y ago
  'south bridge' serial I/O bus (I'm thinking like four LVDS channels clocked at 100MHz) You mean something like https://en.wikipedia.org/wiki/Direct_Media_Interface https://en.wikipedia.org/wiki/Direct_Media_Interface ?
  - ChuckMcM 5y ago
    Yes, although I'd go with the original (and simpler) Intel Hub Architecture concepts. Interestingly enough you can do this on your own using the RISC-V architecture and FPGA's with high speed serial transceivers. So it isn't like you have to be a chip company to build something like it, it just means you're willing to spend way more to implement a RISC-V system than you technically "have" to :-). Esden tweeted today (https://twitter.com/esden/status/1420498544960557062 https://twitter.com/esden/status/1420498544960557062) they have Linux running on the ICE40UP5K which is pretty amazing. That FPGA only has a few LVDS pins so it would be challenging!

pjmlp 5y ago

Indeed, that is why when people think the only way to code these chips is Assembly and C, while we were already using multiple languages on the PCs, shows how there is some kind of misunderstanding of their capabilities. Heck, compiled xBase applications were hardly a speed daemon, yet they were fast enough for what businesses needed of them.