I have been doing semiconductor digital physical design for over 20 years The Verilog RTL for the digital portions of the design are often identical for the sa

I have been doing semiconductor digital physical design for over 20 years The Verilog RTL for the digital portions of the design are often identical for the same design in 2 different foundry processes. The combinational logic gates (AND/OR, registers, etc) are made out of transistors and the transistors are different so all of the logic cells are different. The foundry gives you a library with these cells. You use a synthesis program to "compile" them from Verilog to logic gates. One foundry may have 16 different types of AND gates of various sizes, drive strength, and power usage. The other foundry may have 14 types but their 14X cell is stronger than the 16X cell of the other foundry. There is no direct mapping between these. One foundry may make all standard cells 200 nm in height. They are then placed in uniform rows by the automatic placer tool (Cadence Innovus or Synopsys IC Compiler) The other foundry made their cells 220 nm in height. The block sizes in your floorplan are now going to be different. One foundry made their process for their internal mobile phone use so they focused on small cells for low power. Now you try to make your $3,000 GPU in this process and it won't work as well. One foundry made metal layers 1-5 thin and 6-10 thicker and 11-15 really big. The other foundry had metal layers 1-6 thin. In your old chip you decided to use metal 6 for a certain power layer. Now it is thin and it isn't good for carrying power but thin wire is better for signals. More stuff to change. It gets even worse for custom analog stuff like a PCIE/USB Serdes or PLL. The rules are even more different. You may need some high voltage area and a larger spacing between that section but the other foundry let you put it closer together. In my experience TSMC is the easiest to work with. They have a huge infrastructure to help external customers. Samsung foundries are mainly used by Samsung so they aren't great to deal with as an external customer. Intel only has external customers for strategic things like Altera which they bought 2 years later. Intel optimizes their DRC rules to make one chip a billion times. Their DRC rules are very restrictive to optimize yield. This takes more people and time. TSMC is optimized for a thousand customers making a thousand different chips. They don't care if your yield is 1% lower and you probably don't either if you can get to market 3 months earlier with 10% fewer employees. For Intel that extra 1% over a billion chips is worth hiring more people to meet those extra DRC rules.