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It doesn't necessarily require a massive design change. The problem is that nearly every aspect of two different processes is different, even when there is supp
by kayson 5y ago
It doesn't necessarily require a massive design change. The problem is that nearly every aspect of two different processes is different, even when there is supposed to be an "easy" migration path, such as when the new process is just an optical shrink of another process.
Specifically, the transistor properties are different, and so are the properties of the tiny metal wires connecting the transistors together. Once you get to the design phase where you're dealing with individual transistors (for analog this is right off the bat; for digital it's once you get to place & route), you spend thousands of hours simulating the behavior of the analog circuits, or the effects of the particular arrangement of digital logic gates, to make sure everything works. When the transistor and wire properties change, you at minimum have to repeat all of that verification
Sometimes, the new process is different enough that an old design no longer works, and it takes a lot of engineering effort to fix it. Other times, a few small tweaks are enough. In some cases, particularly for digital-only ICs, the foundry will validate the migration between two processes, essentially saying, "we guarantee the IC you already designed will just work in this new process". Smaller companies might just go with it and accept any yield fallout, but bigger companies like Qualcomm would probably do their own independent verification.
- x0x0 5y agoso if I can summarize -- what we think of as a logical transistor starts to have all sorts of physical properties, some dictated by the material, the physical layout, and probably what's near it. Designers spend piles of time simulating this, and a process change requires that work to be redone. Thanks again!
- mih 5y agoYou got it right. Translating from a logical design to a physical design requires following rules laid out by a foundry for a given process node (5nm, 7nm etc.). To check if a physical layout confirms to a node, Design Rule Checking [1] is performed as part of the Physical Verification step in EDA [2]. The simulation/checking is highly complex and takes hours (sometimes days) even with sufficient parallelization. Once a design passes the checks, it is deemed ready for manufacture by the foundry. [1] https://en.wikipedia.org/wiki/Design_rule_checking https://en.wikipedia.org/wiki/Design_rule_checking [2] https://en.wikipedia.org/wiki/Electronic_design_automation#Analysis_and_verification https://en.wikipedia.org/wiki/Electronic_design_automation#A...
- x0x0 5y agoty!