CISC vs. RISC, bah! My text editor is implemented as a single CPU opcode! It's KiloMegaGigaTeraCISC. You should see the silicon that implements the web browser

CISC vs. RISC, bah! My text editor is implemented as a single CPU opcode! It's KiloMegaGigaTeraCISC. You should see the silicon that implements the web browser instruction. KMGTCISC may not dispatch many ops per second, but what ops they are!