ribit and others are correct. While this may have been possible in the past, at modern memory frequencies and timings, it's not really plausible to deviate from

ribit and others are correct. While this may have been possible in the past, at modern memory frequencies and timings, it's not really plausible to deviate from what the platforms are designed for: LPDDR being soldered and placed a specific layout area relative to the CPU, and for socketed DDR, the sockets being placed in one of a few placements relative to the CPU, with a little layout wiggle room. Edit: I guess to clarify, the plausibility challenge is that whether or not it is theoretically possible, the platform owner (Intel, AMD, etc) or the memory vendors (Samsung, SK Hynix, Micron) are unlikely to support the lark.