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Warp-V: A RISC-V CPU Core Generator Supporting MIPS ISA
- LoveLeadAcid 5y agoHard to extract any useful information from that blog post. Was it written by a bot? EDIT: I am the article writer’s father.
- rahen 5y agoInteresting. Anyone knows what's the benefit of TL-Verilog compared to a next gen HDL like nmigen? Robert Baruch used it extensively for his own RISC-V CPU implementation. Its channel is well worth watching for those interested in CPU design. https://www.youtube.com/c/RobertBaruch/videos https://www.youtube.com/c/RobertBaruch/videos
- mhh__ 5y agoThey have a good summary of the language and why it is what it is on their website. What makes nmigen next gen? Is it even strictly a HDL?