4 ms·

Strange, op-amps (if you don't dive into pushing them to their limits, and if you steer clear of trying to understand how they are implemented) are actually a l

Strange, op-amps (if you don't dive into pushing them to their limits, and if you steer clear of trying to understand how they are implemented) are actually a lot simpler to grok than - say - an NPN transistor.

GeorgeTirebiter 5y ago
Well.... yes, and. If you think of an NPN transistor as a current-operated switch (e.g. to drive an LED or relay), then you can have a pretty simple model of said NPN transistor. If you want to make a low-noise PIN diode photodetector amplifier with an op amp, you want to understand noise per root Hz, input offset voltages, variations with temperature, gain, frequency and phase response, and so much more. So, as is often the case in Engineering: It Depends...
analog31 5y ago
Bipolar (NPN and PNP) circuits can be analyzed by applying the following rules: 1. If current flows through the base-emitter junction, then there is a voltage of roughly 0.6 V across that junction. 2. The collector current is roughly proportional to the base current, by the beta constant, which is about 10 for big transistors and 100 for little ones. There are some rare textbook cases such as logarithmic amplifiers that just have to be looked up, following the Ebers-Moll equation. As for FETs... once you get the type correct (P or N type, enhancement or depletion mode, which I still have to look up or find an example circuit), gate-source voltage is constant, gate current is zero, and the drain current equals the source current. As for vacuum triodes... they behave much like N type JFETs. You can check your analysis of any of these circuits using the wonderful LTSpice.
- exmadscientist 5y ago
  > As for FETs... once you get the type correct (P or N type, enhancement or depletion mode, which I still have to look up or find an example circuit) I used to have this problem too. Turns out it's easier to work with than you think: the symbol actually describes things pretty well. (This ought to be illustrated, but unfortunately I haven't got the time for that.) JFETs are pretty easy. They're always depletion devices, so their channel always starts conducting: it's solid on the symbol. The gate is directly connected to the channel, so it touches, it's symmetrical, so we draw the gate in the center (though I will draw it near one terminal if I am trying to communicate "hey reader, this one is the source, look at it first"), and there's a "diode arrow" that has either N-type material at the channel end (N-channel part!) or P-type material at the channel end (P-channel part!). MOSFETs are more confusing, but it still isn't bad. They're actually four-terminal devices; we'll add the body in a moment. But their defining feature is that insulated gate, so we can show that by pulling the gate away from the channel, drawing it as a solid line running parallel to the channel. The gate comes off it next to the source, to reinforce the idea that V_GS is the controlling voltage here. The body (also called bulk or substrate, though be careful with that last one as it is not actually the substrate in all processes) is what the channel gets formed out of, so let's add the body terminal as coming out of the middle of the channel. The body diode is now formed between the channel and the body proper. We draw it relative to the channel: for N-channel parts, draw the "diode arrow" with the N-type material at the channel and the P-type material at the body terminal, or vice versa for a P-channel part. The body gets tied off to the source in the vast, vast majority of MOSFETs (and indeed this sometimes is part of what singles out one terminal as the source), so we can do that right now by drawing a line between them. We've now made everything we need to draw the symbol of or to explain a depletion MOSFET that works rather like the JFETs previously discussed. But most MOSFETs aren't depletion mode, they're enhancement mode. And so we indicate that by drawing the channel as a dashed line, rather than solid. Since there are three terminals, attached to the channel, D, B, and S, we draw the channel as three dashes, one for each terminal. Now we're done. Walking through that exercise really helped me understand just what these critters are inside and why we draw them the way we do. I hope it helps someone else, too. And I especially hope it might inspire any analog designer who doesn't draw things correctly, perhaps preferring the simplified symbols created by the simplified disciplines (cough digital cough) who can ignore that such things as "linear mode" operation even exist, to draw things using the correct symbols, which are complicated because they tell a rather complicated device's story. (Bonus factoid: ever wonder why P-channel depletion MOSFETs don't exist? As far as I've been able to put together, they do exist. It's just that when you try to manufacture them in the usual processes, the process inevitably causes you to end up with charge trapped under the gate... which turns the poor things off for you. So they're back to being enhancement mode! This effect doesn't bother N-channel parts, since it happens to try to turn them on. I believe this effect can be overcome with careful process control, but no one thinks it would be profitable to bring discrete devices into mass manufacturing. A few integrated parts with P-channel depletion FETs inside have shipped in full volume for decades.)
- ur-whale 5y ago
  > You can check your analysis of any of these circuits using the wonderful LTSpice. I agree that LTSpice is wonderful. It would be even more wonderful if it was open sourced. But because it's been closed source, it has basically stagnated for the past 10 years. But then, this whole notion of sharing your blueprints and designs with the whole world so the whole world can improve them is such a gigantic impedance mismatch with the culture of the EE crowd in general that its quite unlikely to ever happen.

GeorgeTirebiter 5y ago

Well.... yes, and. If you think of an NPN transistor as a current-operated switch (e.g. to drive an LED or relay), then you can have a pretty simple model of said NPN transistor. If you want to make a low-noise PIN diode photodetector amplifier with an op amp, you want to understand noise per root Hz, input offset voltages, variations with temperature, gain, frequency and phase response, and so much more. So, as is often the case in Engineering: It Depends...

analog31 5y ago

Bipolar (NPN and PNP) circuits can be analyzed by applying the following rules: 1. If current flows through the base-emitter junction, then there is a voltage of roughly 0.6 V across that junction. 2. The collector current is roughly proportional to the base current, by the beta constant, which is about 10 for big transistors and 100 for little ones. There are some rare textbook cases such as logarithmic amplifiers that just have to be looked up, following the Ebers-Moll equation. As for FETs... once you get the type correct (P or N type, enhancement or depletion mode, which I still have to look up or find an example circuit), gate-source voltage is constant, gate current is zero, and the drain current equals the source current. As for vacuum triodes... they behave much like N type JFETs. You can check your analysis of any of these circuits using the wonderful LTSpice.

exmadscientist 5y ago
> As for FETs... once you get the type correct (P or N type, enhancement or depletion mode, which I still have to look up or find an example circuit) I used to have this problem too. Turns out it's easier to work with than you think: the symbol actually describes things pretty well. (This ought to be illustrated, but unfortunately I haven't got the time for that.) JFETs are pretty easy. They're always depletion devices, so their channel always starts conducting: it's solid on the symbol. The gate is directly connected to the channel, so it touches, it's symmetrical, so we draw the gate in the center (though I will draw it near one terminal if I am trying to communicate "hey reader, this one is the source, look at it first"), and there's a "diode arrow" that has either N-type material at the channel end (N-channel part!) or P-type material at the channel end (P-channel part!). MOSFETs are more confusing, but it still isn't bad. They're actually four-terminal devices; we'll add the body in a moment. But their defining feature is that insulated gate, so we can show that by pulling the gate away from the channel, drawing it as a solid line running parallel to the channel. The gate comes off it next to the source, to reinforce the idea that V_GS is the controlling voltage here. The body (also called bulk or substrate, though be careful with that last one as it is not actually the substrate in all processes) is what the channel gets formed out of, so let's add the body terminal as coming out of the middle of the channel. The body diode is now formed between the channel and the body proper. We draw it relative to the channel: for N-channel parts, draw the "diode arrow" with the N-type material at the channel and the P-type material at the body terminal, or vice versa for a P-channel part. The body gets tied off to the source in the vast, vast majority of MOSFETs (and indeed this sometimes is part of what singles out one terminal as the source), so we can do that right now by drawing a line between them. We've now made everything we need to draw the symbol of or to explain a depletion MOSFET that works rather like the JFETs previously discussed. But most MOSFETs aren't depletion mode, they're enhancement mode. And so we indicate that by drawing the channel as a dashed line, rather than solid. Since there are three terminals, attached to the channel, D, B, and S, we draw the channel as three dashes, one for each terminal. Now we're done. Walking through that exercise really helped me understand just what these critters are inside and why we draw them the way we do. I hope it helps someone else, too. And I especially hope it might inspire any analog designer who doesn't draw things correctly, perhaps preferring the simplified symbols created by the simplified disciplines (cough digital cough) who can ignore that such things as "linear mode" operation even exist, to draw things using the correct symbols, which are complicated because they tell a rather complicated device's story. (Bonus factoid: ever wonder why P-channel depletion MOSFETs don't exist? As far as I've been able to put together, they do exist. It's just that when you try to manufacture them in the usual processes, the process inevitably causes you to end up with charge trapped under the gate... which turns the poor things off for you. So they're back to being enhancement mode! This effect doesn't bother N-channel parts, since it happens to try to turn them on. I believe this effect can be overcome with careful process control, but no one thinks it would be profitable to bring discrete devices into mass manufacturing. A few integrated parts with P-channel depletion FETs inside have shipped in full volume for decades.)
ur-whale 5y ago
> You can check your analysis of any of these circuits using the wonderful LTSpice. I agree that LTSpice is wonderful. It would be even more wonderful if it was open sourced. But because it's been closed source, it has basically stagnated for the past 10 years. But then, this whole notion of sharing your blueprints and designs with the whole world so the whole world can improve them is such a gigantic impedance mismatch with the culture of the EE crowd in general that its quite unlikely to ever happen.