3 ms·
> That table shows that the M1 has a much bigger reorder buffer, large load and store buffers, huge integer and vector register files, way more branches in flig
by saati 5y ago
> That table shows that the M1 has a much bigger reorder buffer, large load and store buffers, huge integer and vector register files, way more branches in flight, etc.
That leaves out the most important thing that enables all of that, the 8-wide symmetric decoder that can feed those. x86_64 cpus only have 5-wide ones, and only the first of those can decode the multi-uops instructions, and even worse there are even more complex instructions that are microcoded.
- dev_tty01 5y agoYes, absolutely right. That decoder is also beastly. Of course, fixed (nearly) length ARM instructions make the problem a lot easier. x86 instruction format and length variance is just ridiculous. Intel has saddled themselves with years of complexity and it has become a big obstacle for them. They have always muscled through it by throwing process innovation at the problem, but recent stumbles leave them trapped in a box of their own creation. Intel is a great company and I expect them to dig out of this, but it is tough right now.