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Why doesn't anyone ever bother to mention that the M1 is a RISC CPU when discussing that it can do more IPS than x86? There are 1024 possible Armv8 instruction

• wmf 5y ago
  In real workloads ARM executes only slightly more instructions than x86.
  • sudosysgen 5y ago
    While true, it does also mean more stress on the reordering system, cache, branches, etc... Than on x86.
• SilverRed 5y ago
  Do number of instructions even matter on modern chips? intel/amd chips don't even use x86 since they break it down in to their own internal RISC via a translation layer? If you have a CPU that breaks one mega x86 instruction in to 100 internal instructions, is that any better than 100 external instructions generated by a compiler?
  • sudosysgen 5y ago
    It does and doesn't. When your CPU is breaking up that instruction you can optimize for the exact way its being broken up at the design because you know what those 100 instructions will be and in what order. You pay for that with more decode. It's a trade-off, but it does mean there is less of a need for the machinery the M1 has more of, somewhat.
  • ithkuil 5y ago
    You have to feed those 100 instructions to the CPU, this takes memory bandwidth, which means you need larger instruction caches. Caches take up most of the space and power on modern hardware
• Taniwha 5y ago
  yes, but many x86 instructions get cracked into multiple risc-like instructions internally - those things that the ARM can't do likely get converted into what are essentially multiple ARM-like instructions. Theoretically this means that x86 instructions are smaller (with better I$ performance), at the expense of larger/slower instruction decode
  • zelon88 5y ago
    I would argue that it is better because it gives you the ability to tier your hardware higher. Low end SKUs like mobile hardware can get less physical components and more abstraction while higher end SKUs like server hardware can have more physical components and less abstraction for greater performance. All still operate under the guise of the highest-common-denominator. It is a lot easier to abstract away complex instructions from x86 (when performance isn't needed) than it is to add physical hardware instructions to ARM (when performance is needed).
    • Taniwha 5y ago
      More isn't always better in CPU design, more means slower clocks, or longer pipelines, neither of which necessarily mean faster CPUs. Any particular implementation of an architecture is a study in tradeoffs - gates are relatively cheap these days, but not much faster - it makes it easier to throw gates at bigger caches and more cores rather than faster ones - faster clocks likely mean longer pipelines which need lots of well predictable branches to perform which skew an implementation to particular types of benchmarks/workloads
• astrange 5y ago
  > Why doesn't anyone ever bother to mention that the M1 is a RISC CPU when discussing that it can do more IPS than x86? This doesn't really matter, RISC is not a real distinction - it just means "kind of like MIPS". They both have complex address operands and 2-operand vs 3-operand is largely aesthetic. x86's stronger memory model is what matters most since it can reorder memory accesses less often.
• acdha 5y ago
  Other people have commented about the increasing blurriness of that distinction over the last couple of decades but also ask why you believe it matters. Yes, M1 can do more instructions per second but it also does quite well on almost all high-level benchmarks. If it was just the case that a bunch of simple instructions were juicing IPS counts, you’d see a big discrepancy between those two metrics like we used to in the 90s. It seems like the most likely explanation for it not being mentioned is that it doesn’t add much to the conversation.
• BackBlast 5y ago
  The biggest difference is that arm has a fixed length for instructions. Meaning apple can predictably feed more decoders than x86 which must finish decodes before knowing where future boundaries are going to be. AMD has admitted to being at our very near the upper limit for x86 decoding. With arm Apple can have and reliably feed more decoders from the incoming stream of instructions. They have built their whole chip around being able to extract parallelism from the huge instruction window.