CPUs don't need to keep the enregistered bits in any particular order. A little endian CPU could very much actually have the whole register stored in most signi

CPUs don't need to keep the enregistered bits in any particular order. A little endian CPU could very much actually have the whole register stored in most significant bit to least significant bit, or vice versa, a big endian CPU could hypothetically even have the registered stored in little endian order, but that would be a bit odd. The part that matters is that references to smaller version of the same registers grab the correct bits, and that memory reads and writes write individual bytes in the little endian order (or big endian for big endian processors). Lastly bit order matters for any form of serial IO, but once again, it does not need to correspond to the internal ordering used by the processor in any way shape or form. The bit ordering in RAM within an individual byte also does not matter. If a CPU picked a random ordering of bits in a byte (like 46170325 instead of the logical 01234567 or 76543210 orderings) everything would just work as long as nothing else was directly connected to the memory bus. In practice even DMA devices are not connected directly to the memory bus, and all memory access goes through the the CPU's DDR memory controller, so it literally could pick whatever order for mapping bits to bytes that it wanted.