The VLSI equivalent version of this is to build a cpu by manually placing the N/P diffusion regions, the gate poly, the metal contacts, and the metal wires in y

The VLSI equivalent version of this is to build a cpu by manually placing the N/P diffusion regions, the gate poly, the metal contacts, and the metal wires in your EDA program. The conclusion is to either export it as a spice model and simulate it electrically, or actually get it fabbed on an old process node. Week 1-2: construct your own standard library of logic cells (I.e. design the layout of the not gates, nand gates, etc). Week 3-4: compose these std cells into latches and flip flops. Week 5-6: verilog implementation of your cpu. Used primarily as a model. Week 7-10: lay out your CPU. Everything from the register file to the ALU. Placed and routed by hand. Week 11: SAPR the instruction decoder/control logic and then integrate it into your custom layout. Ok so you can’t brag about your layout being 100% custom anymore, but you learned more by doing it this way :P Week 12: write an assembler; compile a simple assembly program. Week 13-14: run it on the CPU; explore the limits of your CPU (clock speed, etc). Well the timeline will vary, but that’s the idea. I think the only feasible way to do that is as a team project spanning multiple quarters. Honestly one of the most rewarding projects I’ve ever done & would recommend to any prof out there who wants to push their students.