3 ms·
According to the Intel developer's manual L1 has parity and all caches up from that have ECC. This would seem to imply that the ring / mesh also has at least pa
by formerly_proven 5y ago
According to the Intel developer's manual L1 has parity and all caches up from that have ECC. This would seem to imply that the ring / mesh also has at least parity (to retry on error). Parity instead of ECC on L1(D) makes sense since the L1(D) has to handle small writes well, while the other caches deal in lines.
- eru 5y agoOf course, parity can only detect an odd number of bit flips.
- RL_Quine 5y agoSome systems do have two parity bits but obviously there’s efficiency loss there.
- namibj 5y agoZen3 has parity on L1I and ECC on L1D and beyond. Even ECC on consumer hardware (it's just a few extra traces on the motherboard).