4 ms·Geohot/twitchcore: A RISC-V core, first in Python, then in Verilog, then on FPGA51 points by lsllc 5y agolsllc 5y agoLivestream (8h20m): https://www.youtube.com/watch?v=camQ9QeBY9Q https://www.youtube.com/watch?v=camQ9QeBY9Qcallesgg 5y agoI think he more or less gave up when he realized he needed a bus width of 38000 bits.coolspot 5y agoGeogot gives me Fabrice Bellard vibes.