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How does ARM solve the splitting of the memory? Just have "number of cores" x "amount of memory"?
by bullen 5y ago
How does ARM solve the splitting of the memory? Just have "number of cores" x "amount of memory"?
- detaro 5y agowhat do you mean by "splitting of the memory"?
- bullen 5y agoLike the article describes, ARM does not have a queue, instead each core has a copy of the memory.
- detaro 5y agoNo, it's a model, it just looks that way to code running on the cores. (E.g. because it is working off a core-local cache that's not immediately synced to all other caches)
- bullen 5y agoAha, but how does the software partition things, wouldn't that require more memory to work? I guess the queue also needs some sort of memory.
- gpderetta 5y agoIt does not. The "partitioning" is only a mental model. This logical partitioning is caused by the physical hardware load and store "queues" [1](and possibly the reorder buffer) which are distinct from the normal coherent caches, and most importantly, are not coherent, causing the illusion of dynamic memory partitioning. Note that the caches themselves do not lead to visible partitioning. On most architectures, even those with very relaxed MM, normal caches are always coherent. While the queue are indeed some sort of memory, I believe (but I'm not an hardware designer) that are implemented differently from static (like cache) and dynamic RAM. Possibly they are just a bunch of microarchitectural hardware register. [1] the term queue is a misnomer because on relaxed MM architectures they are not FIFO.
- vlovich123 5y agoDoes ARM do cache snooping? That used to be how they kept coherency but I don't recall what the more modern techniques were to maintain coherency across CPUs in a NUMA architecture(IIRC snooping doesn't scale well, but maybe they still do a variant).