> This means Rosetta 2 doesn't even have to convert x86 to ARM fully, but instead can convert x86 binaries into a hybrid of x86 and ARM together and can skip st

> This means Rosetta 2 doesn't even have to convert x86 to ARM fully, but instead can convert x86 binaries into a hybrid of x86 and ARM together and can skip steps like memory reordering that Microsoft's translator has to do. I mean, there's no real "hybrid" thing going on at all, it's just a matter of what instructions get emitted by the compiler to match the externally observable semantics. In fact are already ARM platforms that use sequential consistency (TSO) for the memory model besides the M1; Nvidia's Jetson platforms are one such example, and a Rosetta-like translation layer on that platform would be able to take advantage of it all the same. I guess it's just a matter of wordsmithing at the end of the day, though!