RISC-V is such a breath of fresh air compared to other ISAs. It's well thought out, elegant, and effectively solves issues other archs have. It kind of reminds

RISC-V is such a breath of fresh air compared to other ISAs. It's well thought out, elegant, and effectively solves issues other archs have. It kind of reminds me of rust in that way actually. More to the point, the LR/SC instructions are an implementation of transactional memory, but only for single words. This is pretty exciting, since transactional memory is a possible way to make writing concurrent programs faster (and make the programs themselves faster).