Sure there are great benefits in sequential access, some of these can even be calculated to some extent. However your reply does not answer the question. Do y

Sure there are great benefits in sequential access, some of these can even be calculated to some extent. However your reply does not answer the question. Do you know of any CPU that has specific instructions to handle cache? How can you be sure that you are gaming cache lines when even the mnemonics are mostly virtualised through all the pipeline and jump/memory pattern predictions?