3 ms·
Do you have an example of this in action? I'd be interested to know what steps are taken to avoid false sharing of cache lines in the ring buffer itself.
by reitzensteinm 5y ago
Do you have an example of this in action? I'd be interested to know what steps are taken to avoid false sharing of cache lines in the ring buffer itself.
- sillysaurusx 5y agoYou pad each counter so that it's on a separate cache line. https://lmax-exchange.github.io/disruptor/ https://lmax-exchange.github.io/disruptor/ goes into detail on the false sharing problem. (A+ and full marks on recognizing that that's a central problem.)
- rigtorp 5y agoI think reitzensteinm was referring to the actual data inside the ring. There is a false sharing problem there particularly for the MPMC type ring buffer like disruptor. The solution is to pad each data slot in addition to the read and write indices. I do this in my MPMC ring buffer queue: https://github.com/rigtorp/MPMCQueue/blob/master/include/rigtorp/MPMCQueue.h#L106 https://github.com/rigtorp/MPMCQueue/blob/master/include/rig...
- rigtorp 5y agoYou can align and pad each ring buffer slot to the cache line size. Example https://github.com/rigtorp/MPMCQueue/blob/master/include/rigtorp/MPMCQueue.h#L106 https://github.com/rigtorp/MPMCQueue/blob/master/include/rig...