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I'm kind of torn on the alternative HDLs. The HDL code they generate is often not very readable. When you're simulating you're effectively debugging that genera
by UncleOxidant 5y ago
I'm kind of torn on the alternative HDLs. The HDL code they generate is often not very readable. When you're simulating you're effectively debugging that generated code. Generate statements in VHDL/System Verilog can often cover some of the use cases. Mostly I find them useful for testbench generation - that seems to be where things like Cocotb really shine.
- tn1 5y agoFor Chisel, the most popular tester Treadle has VCD dumps built in. That way you can do your behavioral debugging directly with the source. Of course, for anything involving timing etc you'll have to go with the relevant vendors' tools, which is typically Verilog/VHDL.