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Intel and AMD do it in the memory controller. The caches, by virtue of being entirely on-die, are assumed to be inaccessible. It is unclear what AMD intends to
by kijiki 5y ago
Intel and AMD do it in the memory controller. The caches, by virtue of being entirely on-die, are assumed to be inaccessible.
It is unclear what AMD intends to do here for their TSV stacked mega-cache thing. Perhaps they'll declare the TSVs as not practically snoopable, similar to how on-die metal layer wires are treated now...
- wmf 5y agoMy concern is less about the die boundary and more about vendor boundaries. In an Arm-based SoC with potentially a bunch of different IP all sharing the coherent fabric do you want to bet that all that IP will correctly implement CCA? Probably not.
- kijiki 5y agoA legit concern. Basically everything that connects directly to the cache controllers has to get CCA right. Coherent GPUs are the big, complicated one. Intel had an SGX bug where the GPU could access the last 16 bytes of every 64 byte cache line. If you need the GPU enabled, you have no choice but to design your enclave to only use the first 48 bytes of each cache line. Fortunately if you don't need the GPU, whether or not the GPU is enabled (among other things) is measured and included in the attestation quote, so clients can simply choose to refuse to talk to servers with the GPU enabled...