3 ms·

The following is speculation on my part, so I'm inviting discussion. To some extent it feels SiFive is trying to turn RISC-V into ARM by locking it up in patent

by chem83 5y ago

The following is speculation on my part, so I'm inviting discussion. To some extent it feels SiFive is trying to turn RISC-V into ARM by locking it up in patents while at the same time holding the keys to the ratification of the various extensions, some of which (H-extensions being good example[1]) have been stuck without much development, slowing down sw support and making it difficult to upstream[2] what has been developed so far. Meanwhile, WorldGuard is available and perhaps thriving as closed, commercial IP. It feels like there could be some conflicts of interest there and, honestly, if Intel bought SiFive, it would at least make those intentions blatantly obvious. [1] https://lwn.net/ml/linux-kernel/CAAhSdy0F7gisk=FZXN7jmqFLVB3456WunwVXhkrnvNuWtrhWWA@mail.gmail.com/ https://lwn.net/ml/linux-kernel/CAAhSdy0F7gisk=FZXN7jmqFLVB3... [2] https://lists.riscv.org/g/tech-privileged/topic/risc_v_h_extension_freeze/80346318?p=,,,20,0,0,0::recentpostdate%2Fsticky,,,20,2,0,80346318 https://lists.riscv.org/g/tech-privileged/topic/risc_v_h_ext...

zozbot234 5y ago
IIRC, H extension was set aside because much of the desiderata for H could be achieved more simply by reusing the S (supervisor mode) extension.
- chem83 5y ago
  Do you happen to have a link to this discussion? I couldn't find anything associated with the spec commits on [1]. One of the aspects folks were looking forward to seeing is the specification of the 2-stage IOMMU, which S-mode or other parts of the spec don't address per the lengthy discussion on [2]. Thanks. [1] https://github.com/riscv/riscv-isa-manual/commits/master/src/hypervisor.tex https://github.com/riscv/riscv-isa-manual/commits/master/src... [2] https://arxiv.org/pdf/2103.14951.pdf https://arxiv.org/pdf/2103.14951.pdf
- nickik 5y ago
  The H-Mode has been removed, but people usually still call it the H extension.
  - chem83 5y ago
    Good point H-mode != H-extension. H-extension is very much still alive, afaik, and that is what I referred to.
csdreamer7 5y ago
> RISC-V into ARM by locking it up in patents while at the same time holding the keys to the ratification of the various extensions Would you please provide a direct link to some of those patents or discussion? The thread at [1] if I read it carefully does not mention patents, but seems to be a prelude to submitting the RISCV kvm stuff to staging that Greg KH complained about a while ago.

by chem83 5y ago

zozbot234 5y ago

IIRC, H extension was set aside because much of the desiderata for H could be achieved more simply by reusing the S (supervisor mode) extension.

chem83 5y ago
Do you happen to have a link to this discussion? I couldn't find anything associated with the spec commits on [1]. One of the aspects folks were looking forward to seeing is the specification of the 2-stage IOMMU, which S-mode or other parts of the spec don't address per the lengthy discussion on [2]. Thanks. [1] https://github.com/riscv/riscv-isa-manual/commits/master/src/hypervisor.tex https://github.com/riscv/riscv-isa-manual/commits/master/src... [2] https://arxiv.org/pdf/2103.14951.pdf https://arxiv.org/pdf/2103.14951.pdf
nickik 5y ago
The H-Mode has been removed, but people usually still call it the H extension.
- chem83 5y ago
  Good point H-mode != H-extension. H-extension is very much still alive, afaik, and that is what I referred to.

csdreamer7 5y ago

> RISC-V into ARM by locking it up in patents while at the same time holding the keys to the ratification of the various extensions Would you please provide a direct link to some of those patents or discussion? The thread at [1] if I read it carefully does not mention patents, but seems to be a prelude to submitting the RISCV kvm stuff to staging that Greg KH complained about a while ago.