> how do you generate recursive designs in vhdl? e.g. reduction trees? >> preprocessing/templating > so your tool (vhdl/verilog) requires using another tool (

> how do you generate recursive designs in vhdl? e.g. reduction trees? >> preprocessing/templating > so your tool (vhdl/verilog) requires using another tool (perl/tcl/python) to be productive and you think that's not a failing of the (first) tool? In my opinion yes it does, and yes that is a failing. But what I was saying is, that alone is not worth the large cost of moving to something new. I was asking if Slice could offer anything more to justify that large cost.