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>what they bring that's so much better how do you generate recursive designs in vhdl? e.g. reduction trees? >preprocessing/templating can't fix so your tool

• kingosticks 5y ago
  > how do you generate recursive designs in vhdl? e.g. reduction trees? >> preprocessing/templating > so your tool (vhdl/verilog) requires using another tool (perl/tcl/python) to be productive and you think that's not a failing of the (first) tool? In my opinion yes it does, and yes that is a failing. But what I was saying is, that alone is not worth the large cost of moving to something new. I was asking if Slice could offer anything more to justify that large cost.
• zsmi 5y ago
  > how do you generate recursive designs in vhdl? I understand mapping a recursive algorithm to hardware, and VHDL can definitely do that [1]. (even if it is generally a bad idea) But what is a recursive hardware design? It sounds really interesting. [1] https://vhdlguru.blogspot.com/2010/04/recursive-functions-in-vhdl.html https://vhdlguru.blogspot.com/2010/04/recursive-functions-in...
  • anon_tor_12345 5y ago
    actually this is exactly what i was talking about i.e. (as far as i understand it) this is essentially a reduction tree. i called it a recursive hardware design because it synthesizes to indeed i was unaware that you recursively call functions in vhdl. thanks!