Current chips are basically 2D. Not quite, in that they do have 3D features, but those 3D features are essentially still implementing individual cells in a 2D

Current chips are basically 2D. Not quite, in that they do have 3D features, but those 3D features are essentially still implementing individual cells in a 2D circuit. And those 2D circuits fit, eg. 4Gbits of DRAM into a single layer chip. The actual chip inside the plastic packaging is quite small -- let's say 4x4mm. Now, you can can pack multiple layers of chips into a single package. Samsung is doing at least 12 layers for HBM, for instance, and they're only 60um thick each. So you've got a chip that is roughly 65536 cells wide, and 65536 cells long, but you can only stack it 12 cells high. Let's get that to 65536 layers: roughly a 4mm cube. That's now 256Tbits per package. Put 36 of those on a DIMM, and you've got an 8PB DIMM, and 512 PB in a 64 DIMM slot server. Perhaps we can double the density? That gives us 4EB in a server. This totally glosses over myriad difficult issues, but it's a very, very long way from being inconceivable when you consider the difference between a 512 byte 2114 RAM chip that was popular when I got my first computer, and what we have today.