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We may end up with 128-bit pointers even without a "true" 128-bit architecture. For example, CHERI has 128-bit pointers with 64-bit address space and 64 bits of
by pornel 5y ago
We may end up with 128-bit pointers even without a "true" 128-bit architecture. For example, CHERI has 128-bit pointers with 64-bit address space and 64 bits of metadata to crash harder on memory bugs in C and C++:
https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/ https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/
- p_l 5y agoAS/400 architecture has been using 128bit pointers for several decades by now, even if underneath it involves 32bit or 64bit cpus - except for a tiny bit of code provided by IBM, you're not allowed to target them directly.
- fanf2 5y agoAnd ARM is working with the CHERI team to make a hardware prototype SOC (not FPGA-based like the MIPS CHERI research devices) https://www.arm.com/company/news/2020/10/morello-program-one-year-on https://www.arm.com/company/news/2020/10/morello-program-one...