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> Of course competent programmers ... And obviously any intelligent CPU architect Interesting to see the future is so "obvious" to you. You are correct however

> Of course competent programmers ... And obviously any intelligent CPU architect Interesting to see the future is so "obvious" to you. You are correct however, that this is not a problem at the present because no architecture uses more then 48-bits of address space in practice. And since this is such a common practice now, there will have to allowances made in the future for when the address space is expanded.

vlovich123 5y ago
As a sibling to you noted, Ice Lake has bumped this from 48 bits to 57 bits to support 5-level paging [1]. So the "in practice" appears to already by out of date. This was known publicly as early as 2017 (albeit this is the first I've heard of it). That being said, I don't know why the increase from 256TB to 128PB is at all useful but it's enabled in my Arch Linux kernel on a 32GB laptop, so clearly adopted by the broader ecosystem even outside whatever niche use-case it's for. That being said, the kernel maintains backward compatability by restricting the allocation address space it hands out by default. Userspace needs to explicitly ask for the higher bits [2], so it's probably OK to just continue as-is assuming the 48-bit limit in practice. [1] https://en.wikipedia.org/wiki/Intel_5-level_paging https://en.wikipedia.org/wiki/Intel_5-level_paging [2] https://www.kernel.org/doc/html/latest/x86/x86_64/5level-paging.html#:~:text=On%20x86%2C%205%2Dlevel%20paging,ready%20to%20handle%20wide%20addresses.&text=Specifying%20high%20hint%20address%20on,from%2047%2Dbit%20address%20space https://www.kernel.org/doc/html/latest/x86/x86_64/5level-pag....