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Google and efabless are offering free IC production for people who want to do open source chip design for what it's worth: https://www.efabless.com/open_shuttle

Google and efabless are offering free IC production for people who want to do open source chip design for what it's worth: https://www.efabless.com/open_shuttle_program https://www.efabless.com/open_shuttle_program This started last summer and a number of interesting designs have been produced, pretty much entirely with free, open source tools. Join the slack and ask around for projects that need help if you want to dip your toes in this sort of work! https://invite.skywater.tools/ https://invite.skywater.tools/

jjoonathan 5y ago
Is it still digital only? I'm interested, but almost entirely on the analog side -- I'd love to design a NLTL, VCO, or distributed amplifier. I have the utmost respect for the crowd looking to scale RISC-V cores, but it's just not my scene. EDIT: I took a look at https://github.com/yrrapt/caravel_amsat_txrx_ic_mpw2 https://github.com/yrrapt/caravel_amsat_txrx_ic_mpw2 and there are clearly some analog projects in there. Evidently I should have hustled harder!
- madengr 5y ago
  No, they have a harness called Caravan that has no I/O buffers. I calculated Ft=65 GHz on this process and have a 1-15 GHz amp working in simulation (pre-extraction), though I don’t know if I’ll have time to apply for the next run.
fxtentacle 5y ago
From reading the documentation, it appears that their open source tools start with Verilog RTL files that have been simulated with Synopsys VCS, Mentor Graphics Questa, or Cadence Incisive Enterprise Simulator. That said, one could probably use the free (but not open source) Vivado HL WebPACK to create and test the RTL design and then follow along with the Skywater tools. But that way, the way towards the FPGA would still be closed source and only the path from FPGA on to ASIC would be open. Further down the rabbit hole, I read about https://github.com/icebreaker-fpga/icebreaker https://github.com/icebreaker-fpga/icebreaker which appears to be a tiny Teensy-compatible open source FPGA board with accompanying open source tools. Yay! Thank you very much for bringing all of this to my attention :)
- madengr 5y ago
  I’m taking the Zero to ASIC course, and it’s a fully open source flow from Verilog to GDS.

jjoonathan 5y ago

Is it still digital only? I'm interested, but almost entirely on the analog side -- I'd love to design a NLTL, VCO, or distributed amplifier. I have the utmost respect for the crowd looking to scale RISC-V cores, but it's just not my scene. EDIT: I took a look at https://github.com/yrrapt/caravel_amsat_txrx_ic_mpw2 https://github.com/yrrapt/caravel_amsat_txrx_ic_mpw2 and there are clearly some analog projects in there. Evidently I should have hustled harder!

madengr 5y ago
No, they have a harness called Caravan that has no I/O buffers. I calculated Ft=65 GHz on this process and have a 1-15 GHz amp working in simulation (pre-extraction), though I don’t know if I’ll have time to apply for the next run.

fxtentacle 5y ago

From reading the documentation, it appears that their open source tools start with Verilog RTL files that have been simulated with Synopsys VCS, Mentor Graphics Questa, or Cadence Incisive Enterprise Simulator. That said, one could probably use the free (but not open source) Vivado HL WebPACK to create and test the RTL design and then follow along with the Skywater tools. But that way, the way towards the FPGA would still be closed source and only the path from FPGA on to ASIC would be open. Further down the rabbit hole, I read about https://github.com/icebreaker-fpga/icebreaker https://github.com/icebreaker-fpga/icebreaker which appears to be a tiny Teensy-compatible open source FPGA board with accompanying open source tools. Yay! Thank you very much for bringing all of this to my attention :)

madengr 5y ago
I’m taking the Zero to ASIC course, and it’s a fully open source flow from Verilog to GDS.