The paper uses a custom memory controller based on SoftMC implemented on an FPGA. The DRAM modules themselves are off-the-shelf. It appears you need precise con

The paper uses a custom memory controller based on SoftMC implemented on an FPGA. The DRAM modules themselves are off-the-shelf. It appears you need precise control over DDR4 command timing that would not be possible with a normal memory controller. So it's hardware-only, though you could imagine adding this feature to memory controllers in the future.