A register based ISA implicitly conveys dependencies between instructions. This allows the CPU to infer which instructions can be executed in parallel (supersc

A register based ISA implicitly conveys dependencies between instructions. This allows the CPU to infer which instructions can be executed in parallel (superscalar execution). Extracting instructions level parallelism (ILP) from a stack oriented is harder, but if a compiler can do it, technically a CPU could do the same. The question is: what would be the advantage? ILP extraction can be done statically. Doing it on a CPU at runtime would cost time and power. OTOH, stack based instruction sets tend to be more compact, so there is less pressure to the memory hierarchy to pull in the code, leaving more bandwidth for operands, and thus reducing stalls. CPU design is a tradeoff in a tradeoff in a tradeoff.