2 ms·

Direct link to whitepaper: https://f.hubspotusercontent30.net/hubfs/8968533/Cerebras-CS-2-Whitepaper.pdf https://f.hubspotusercontent30.net/hubfs/8968533/Cereb

• mikewarot 5y ago
  No actual specifications about precision of computations, operations supported, etc., just impressive I/O numbers.
  • tyingq 5y ago
    There's better info here: https://blog.inten.to/hardware-for-deep-learning-part-4-asic-96a542fe6a81#3e5b https://blog.inten.to/hardware-for-deep-learning-part-4-asic... "The instruction set supports operations on INT16, FP16, and FP32 types. Floating-point adds, multiplies, and fused multiply-accumulate (or FMAC, with no rounding of the product prior to the add) can occur in a 4-way SIMD manner for 16-bit operands. The instruction set supports SIMD operations across subtensors of four-dimensional tensors, making use of tensor address generation hardware to efficiently access tensor data in memory." The source appears to be this PDF: https://arxiv.org/pdf/2010.03660.pdf https://arxiv.org/pdf/2010.03660.pdf