The BIOS on an AMD reference platform refers to there being 1, 2, or 4 "X3D stacks", suggesting that eventually you might be talking about more cache than this:

The BIOS on an AMD reference platform refers to there being 1, 2, or 4 "X3D stacks", suggesting that eventually you might be talking about more cache than this: https://twitter.com/aschilling/status/1399701274489151489 https://twitter.com/aschilling/status/1399701274489151489 (Who knows when/if they get 2/4-high working and at what price: the I/O die needs to be able to track tags proportionate to the total cache size, the compute chiplet needs to support it, and packaging/power/everything else needs to work out. Switch in BIOS doesn't mean the rest is there.) Other clever thing about this for them is they can keep focusing on one base compute chiplet but turn it into a wider range of SKUs, on top of how they already do that with core count etc. Same chiplet can end up in a product with 32 or 96MB L3/CCD as soon as the first two-high stack comes out and, obviously, more if/when they get 2/4-high going.